A delay line is used to produce a number of digital signals, each one delayed in time with respect to each other. Applications of delay lines include but are not limited to clock generation, Finite Impulse Response filters, and clock recovery. A classic delay line structure 10 and its output signals are shown in FIGS. 1a and 1b. In this classical delay line structure 10, a chain of unit delay cells 12 with a known propagation delay are cascaded together, resulting in the unit output delay being determined by the propagation delay of each of the unit delay cells 12. At the board level, devices such as Surface Acoustic Wave (SAW) devices or piezoelectric quartz crystals are available which produce high-accuracy delay times. However, for delays which must be incorporated on a semiconductor chip, only standard semiconductor devices are available.
The simplest on-chip delay line is a chain of cascaded inverters shown in FIG. 2 as pairs of pMOS devices 16 and nMOS devices 14. The key advantage of such circuits is their speed: they are the fastest unit circuits available which produce full-rail outputs. Their key disadvantage is the extreme variability of the inverter propagation delays with process, temperature and power supply voltage. Variations of -50% to +100% of nominal propagation delays are not unusual. In addition, controlling this delay line may be difficult as it would involve modulation of the power supply voltage. Such modulation would, in turn, require that additional circuitry be included which translates the inverter outputs to full-rail CMOS outputs.
A better delay line structure is the so-called "starved inverter" structure, shown in FIG. 3. The bias current source 20 sets the currents through the diode-connected pMOS 22 and nMOS 42 transistors and generate bias voltages. A bias voltage is thus supplied from the pMOS transistor 22 to the replica pMOS transistors 24, 26, and 28, setting the current through transistors 24, 26 and 28 to mirror the bias current 20. Similarly, the bias voltage from the nMOS transistor 42 is applied to the replica nMOS transistors 44, 46 and 48 so that the current through the latter transistors mirrors that of current source 20. The remainder of the circuit comprising transistors 30, 32, 34, 36, 38, and 40 is configured as the inverter chain delay line of FIG. 2. This circuit produces full-rail CMOS outputs and is controllable by modulating the input bias current source, however, mismatches between the n-channel and p-channel current sources or in inverter threshold voltages will appear as delay mismatches in the outputs. Since this circuit's unit delays are now mainly determined by currents and capacitances, not the internal structure of the CMOS inverter, the delays generated by this circuit show less variation with process, temperature and voltage. Typically, the bias current will be generated by an on-chip resistor and voltage reference, so the unit delay is a function of an RC delay, which given appropriate component types, can be controlled to within .+-.20%, sufficient for many applications.
Additional implementations are possible using reduced-swing, source-coupled or current-mode logic styles. These all have the advantage of speed (compared to either of the circuits of FIGS. 2 or 3), but may require large DC power dissipation or require additional control circuitry in order to produce a low sensitivity controlled delay.
A major shortcoming of all delay cells based on the architecture of FIG. 1 is a process-imposed minimum propagation delay per stage, and, as a result, these circuits have a minimum unit delay. It is impossible to synthesize a unit delay smaller than the propagation delay through the cells traversed as the limit is set by the CMOS process and is therefor a process-imposed limit. In order to produce a unit delay smaller than this minimum, other techniques must be used. A circuit which uses an RC ladder network to synthesize a particular unit delay, is shown in FIG. 4. In this circuit the input is coupled by a buffer amplifier 60 to a first RC network made up of resistor 72 and capacitor 64. The output is taken through buffer amplifier 62. Similar RC networks made up of resistors 74, 76, and 78 and corresponding capacitors 66, 68, and 70, respectively, in cascade, provide additional delays. Additional outputs are taken through buffer amplifiers 63, 64, and 66. In this circuit, the delay is synthesized by cascaded RC delays which, as described earlier, can be controlled to within .+-.20%. While this circuit can synthesize delays which are smaller than the minimum propagation delay available in a given technology, this technique requires additional analog circuitry to convert the RC network outputs into digital signals, which can require significant DC power. Finally, in order to create a controllable delay line, either the resistances or the capacitances must be controllable, increasing the complexity of the circuit and increasing the sensitivity of the circuit to process, temperature and voltage variations.
Accordingly, it is an object of the invention to provide a delay circuit that can synthesize a unit delay time smaller than the minimum propagation delay of a single unit delay cell. It is a further object of the invention to provide an easily-controlled delay line structure whose delay can be modulated between 100 ps and 1 ns using digital inputs. It is yet a further object of the invention to provide a delay line circuit that can accept differential CMOS inputs and produce differential CMOS outputs. Another object is to provide a circuit that minimizes DC power dissipation of the delay line. Finally, it is an object of the invention to provide a delay line circuit that minimizes the sensitivity of the unit delay to process, voltage and temperature.